At time 75, after asking for the shift, I got the correct sout but the value in the register should have been 0x14 and not 0x02. I meant to do a shift right but specified a shift left instead. $time, reset, sin, inbus, mode, value, value, sdata) Psregister r1 (sin, inbus, clk, mode, reset, value, sdata) initial * Do loads for just two of the changes then start a shift at 69 */ # 11 reset = 1 /* Comes out of reset at time 28 */Įnd /* Change the value on the input bus every so often */ Reg sin = 0 /* Make a reset that pulses once. #4 bit serial parallel converter fsm serial* We need input bus and clock, mode, serial in, and reset as inputs */ Module test /* Make reg inputs and wire outputs for register */ module psregister(pin, clk, load, shift, reset, pout, sout) In order to do this the input shift registers are loaded parallely with the values of bits is added by the adder FSM and at the end of the cycle the recounting sum bit shifted into the sum register. Test for parallel/serial in-out register modeled on 74194. This addition process starts by adding bits a0 and b0 then in the next clock cycle bits a1 and b1 are added, which is also added with the carry from the bit position 0 and so on. I ran it with a slightly modified version of the previous test. Wire sin, pin, clk, mode, reset always clk) Module psregister(sin, pin, clk, mode, reset, pout, sout) parameter WIDTH = 8 output pout reset : asynchronous reset to zero (active low) ![]() mode : mode control 0 hold, 1 shl, 2 shr, 3 load ė4194 universal shift register but extended to arbitrary number ![]() ![]() load & shift and asynchronous clear (reset). Parallel-in, parallel-out, serial out register with synchronous
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